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HSM
 
What does 'Post Code' mean?

Extract from IBM manual:

28.0 POST -- Signal Event Completion
Use the POST macro to set a specified event control block (ECB) to indicate the occurrence of an event. If this event satisfies the requirements of an outstanding WAIT or EVENTS micro, the waiting task is taken out of the wait state and dispatched according to its priority.

The bits in the ECB are set as follows:
Bit 0 of the specified ECB is set to 0 (wait bit).
Bit 1 is set to 1 (complete bit).
Bits 2 through 31 are set to the specified completion code.

The POST macro is also described in MVS/ESA SP V5 Assembler Services

Reference with the exception of the ASCB, ERRET, and ECBKEY authorized parameters. For further information on how to use POST to serialize parallel tasks, see MVS/ESA SP V5 Auth Assembler Services Guide.

POST CODE
The post code is not issued by SRM but by the IBM channel I/O.


 

 



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